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1 features ? low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 3.6v) internally organized 65,536 x 8 two-wire serial interface schmitt triggers, filtered in puts for noise suppression bidirectional data transfer protocol 1 mhz (5v), 400 khz (2.7v) and 100 khz (1.8v) compatibility write protect pin for hardware and software data protection 128-byte page write mode (partial page writes allowed) self-timed write cycle (5 ms max) high reliability ? endurance: 100,000 write cycles ? data retention: 40 years automotive grade, extended temp erature and lead-free/halogen-free devices available 8-lead pdip, 8-lead eiaj soic, 8- lead jedec soic, 8-lead tssop, 8-lead lap, 8-lead sap and 8-ball dbga2 packages die sales: wafer form, waffle pack and bumped die description the at24c512 provides 524,288 bits of serial electrically erasable and programmable read only memory (eeprom) organized as 65,536 words of 8 bits each. the device?s cascadable feature allows up to four devices to share a common two-wire bus. the device is optimized for use in many industrial and commercial applications where low- power and low-voltage operation are essential. the devices are available in space- saving 8-pin pdip, 8-lead eiaj soic, 8- lead jedec soic, 8-lead tssop, 8-lead leadless array (lap), and 8-lead sap packages. in addition, the entire family is avail- able in 2.7v (2.7v to 5.5v) and 1.8v (1.8v to 3.6v) versions. table 1. pin configurations pin name function a0?a1 address inputs sda serial data scl serial clock input wp write protect nc no connect rev. 1116m?seepr?05/05 two-wire serial eeprom 512k (65,536 x 8) at24c512 8-lead pdip 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-lead leadless array bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda a0 a1 nc gnd 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-lead sap bottom view 1 2 3 4 8 7 6 5 vcc wp scl sda a0 a1 nc gnd 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 nc gnd vcc wp scl sda 8-ball dbga2 bottom view vcc wp scl sda a0 a1 nc gnd 1 2 3 4 8 7 6 5
2 at24c512 1116m?seepr?05/05 figure 1. block diagram absolute maximum ratings* operating temperature..................................?55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65 c to +150 c voltage on any pin with respect to ground .............. ...................... ?1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma
3 at24c512 1116m?seepr?05/05 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/addresses (a1, a0): the a1 and a0 pins are device address inputs that are hardwired or left no t connected for hardware compatib ility with other at24cxx devices. when the pins are hardwired, as many as four 512k devices may be addressed on a single bus system (device addressing is discussed in detail under the device address- ing section . if the pins are left floating, the a1 and a0 pins will be internally pulled down to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends connecting the address pins to gnd. write protect (wp): the write protect input, when connected to gnd, allows nor- mal write operations. when wp is connected high to v cc , all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled down to gnd if the capacitive coupling to the circuit board v cc plane is <3 pf. if coupling is >3 pf, atmel recommends connecting the pin to gnd. switching wp to v cc prior to a write operation creates a software write protect function. memory organization at24c512, 512k serial eeprom: the 512k is internally organized as 512 pages of 128-bytes each. random word addressing requires a 16-bit data word address.
4 at24c512 1116m?seepr?05/05 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +1.8v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , scl) 6 pf v in = 0v table 3. dc characteristics applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +1.8v to +5.5v, t ac = 0 c to +70 c, v cc = +1.8v to +5.5v (unless otherwise noted) symbol parameter test co ndition min typ max units v cc1 supply voltage 1.8 3.6 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v read at 400 khz 1.0 2.0 ma i cc2 supply current v cc = 5.0v write at 400 khz 2.0 3.0 ma i sb1 standby current (1.8v option) v cc = 1.8v v in = v cc or v ss 1.0 a v cc = 3.6v 3.0 i sb2 standby current (2.7v option) v cc = 2.7v v in = v cc or v ss 2.0 a v cc = 5.5v 6.0 i sb3 standby current (5.0v option) v cc = 4.5 - 5.5v v in = v cc or v ss 6.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ?0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.8v i ol = 0.15 ma 0.2 v
5 at24c512 1116m?seepr?05/05 notes: 1. this parameter is characterized and is not 100% tested. 2. ac measurement conditions: r l (connects to v cc ): 1.3 k ? (2.7v, 5v), 10 k ? (1.8v) input pulse voltages: 0.3v cc to 0.7v cc input rise and fall times: 50 ns input and output timing reference voltages: 0.5v cc 3. the write cycle time of 5 ms only applies to the at24c512 devices bearing the process le tter ?a? on the package (the mark is located in the lower right corner on the top side of the package). table 4. ac characteristics applicable over recommended operating range from t a = ? 40 c to +85 c, v cc = +1.8v to +5.5v, c l = 100 pf (unless oth- erwise noted) test conditions are listed in note 2. symbol parameter 1.8 volt 2.7 volt 5.0 volt units min max min max min max f scl clock frequency, scl 100 400 1000 khz t low clock pulse width low 4.7 1.3 0.4 s t high clock pulse width high 4.0 1.0 0.4 s t aa clock low to data out valid 0.1 4.5 0.05 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start (1) 4.7 1.3 0.5 s t hd.sta start hold time 4.0 0.6 0.25 s t su.sta start set-up time 4.7 0.6 0.25 s t hd.dat data in hold time 0 0 0 s t su.dat data in set-up time 200 100 100 ns t r inputs rise time (1) 1.0 0.3 0.3 s t f inputs fall time (1) 300 300 100 ns t su.sto stop set-up time 4.7 0.6 0.25 s t dh data out hold time 100 50 50 ns t wr write cycle time 20 or 5 (3) 10 or 5 (3) 10 or 5 (3) ms endurance (1) 5.0v, 25 c, page mode 100k 100k 100k write cycles
6 at24c512 1116m?seepr?05/05 device operation clock and data transitions: the sda pin is normally pulled high with an exter- nal device. data on the sda pin may change only during scl low time periods (see figure 4 on page 7). data c hanges during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 5 on page 8). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 5 on page 8). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero during the ninth clock cycle to acknowledge that it has received each word. standby mode: the at24c512 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two- wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda high in each cycle while scl is high and then (c) create a start condition as sda is high.
7 at24c512 1116m?seepr?05/05 figure 2. bus timing (scl: serial clock, sda: serial data i/o) figure 3. write cycle timing (scl: serial clock, sda: serial data i/o) note: 1. the write cycle time t wr is the time from a valid stop condition of a write s equence to the end of the internal clear/write cycle. figure 4. data validity t wr (1) stop condition start condition wordn ack 8th bit scl sda
8 at24c512 1116m?seepr?05/05 figure 5. start and stop definition figure 6. output acknowledge
9 at24c512 1116m?seepr?05/05 device addressing the 512k eeprom requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see figure 7 on page 10). the device address word consists of a mandatory ?1?, ?0? sequence for the first five most significant bits as shown. this is commo n to all two-wir e eeprom devices. the 512k uses the two device address bits a1 , a0 to allow as many as four devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write operation select bit. a read opera- tion is initiated if this bit is high and a writ e operation is initiated if this bit is low. upon a compare of the device address, th e eeprom will output a ?0?. if a compare is not made, the devi ce will return to a standby state. data security: the at24c512 has a hardware data protection scheme that allows the user to write protect the whole memory when the wp pin is at v cc . write operations byte write: a write operation requires two 8-bit data word addresses following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a ?0? and then clock in the first 8-bi t data word. fo llowing receipt of the 8-bit data word, the eeprom will output a ?0?. the add ressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. at this time the eeprom enters an inte rnally-timed wr ite cycle, t wr , to the nonvolatile memory. all inputs are disabled during this writ e cycle and the eeprom will not respond until the write is complete (see figure 8 on page 11). page write: the 512k eeprom is capable of 128-byte page writes. a page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 127 more data words. the eeprom will respond with a ?0? after each data word received. the microcontroller must terminate the page write sequence with a stop condition (see figure 9 on page 11). the data word address lower 7 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 128 data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be ov erwritten. the address roll over during write is from the last byte of the current page to the first byte of the same page. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabl ed, acknowledge polling can be in itiated. this involves send- ing a start condition followed by the dev ice address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ?0?, allowing the read or write se quence to continue.
10 at24c512 1116m?seepr?05/05 read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to ?1?. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by ?1?. this address stays valid between operations as long as the chip power is maintained. the address roll over during read is from the last byte of the last memory page, to the first byte of the first page. once the device address with the read/write select bit set to ?1? is clocked in and acknowledged by the eeprom, the current addr ess data word is serially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition (see figure 10 on page 11). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit hi gh. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a ?0? but does generate a following stop condition (see figure 11 on page 11). sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom re ceives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reac hed, the data word address will roll over and the sequential read will continue. the sequential read operation is te rminated when the microcontroller does not respond with a ?0? but does generate a following stop condition (see figure 12 on page 12). figure 7. device address
11 at24c512 1116m?seepr?05/05 figure 8. byte write figure 9. page write figure 10. current address read figure 11. random read
12 at24c512 1116m?seepr?05/05 figure 12. sequential read
13 at24c512 1116m?seepr?05/05 notes: 1. for 2.7v devices used in the 4.5v to 5.5v range, pleas e refer to performance values in the ac and dc characteristics ta bles. 2. ?u? designates green package + rohs compliant. 3. available in waffle pack and wafer form; order as sl719 for wafer form. bumped die available upon request. please contact serial eeprom marketing. ordering information (1) ordering code package operation range at24c512c1-10ci-2.7 at24c512-10pi-2.7 at24c512w-10si-2.7 at24c512n-10si-2.7 at24c512-10ti-2.7 8cn1 8p3 8s2 8s1 8a2 industrial temperature (?40 c to 85 c) at24c512c1-10ci-1.8 at24c512-10pi-1.8 at24c512w-10si-1.8 at24c512n-10si-1.8 at24c512-10ti-1.8 8cn1 8p3 8s2 8s1 8a2 industrial temperature (?40 c to 85 c) at24c512c1-10cu-2.7 (2) at24c512c1-10cu-1.8 (2) at24c512-10pu-2.7 (2) at24c512-10pu-1.8 (2) at24c512w-10su-2.7 (2) at24c512w-10su-1.8 (2) at24c512n-10su-2.7 (2) at24c512n-10su-1.8 (2) at24c512-10tu-2.7 (2) at24c512-10tu-1.8 (2) at24c512y4-10yu-1.8 (2) at24c512u4-10uu-1.8 (2) 8cn1 8cn1 8p3 8p3 8s2 8s2 8s1 8s1 8a2 8a2 8y4 8u4-1 lead-free/halogen-free/ industrial temperature (?40 c to 85 c) at24c512-w2.7-11 (3) at24c512-w1.8-11 (3) die sale die sale industrial temperature (?40 c to 85 c) package type 8cn1 8-lead, 0.300" wide, leadless array package (lap) 8p3 8-lead, 0.300" wide, plastic dual in-line package (pdip) 8s2 8-lead, 0.200? wide, plastic gull wing small outline package (eiaj soic) 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) 8y4 8-lead, 6.00 mm x 4.90 mm body, dual footpr int, non-leaded, small array package (sap) 8u4-1 8-ball, die ball grid array package (dbga2) options ?2.7 low-voltage (2.7v to 5.5v) ?1.8 low-voltage (1.8v to 3.6v)
14 at24c512 1116m?seepr?05/05 packaging information 8u4-1 ? dbga2 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. po8u4-1 a 1/5/05 common dimensions (unit of measure = mm) symbol min nom max note 8u4-1, 8-ball, 2.47 x 4.07 mm body, 0.75 mm pitch, small die ball grid array package (dbga2) a 0.81 0.91 1.00 a 1 0.15 0.20 0.25 a 2 0.40 0.45 0.50 b 0.25 0.30 0.35 d 2.47 bsc e 4.07 bsc e 0.75 bsc e1 0.74 ref d 0.75 bsc d1 0.80 ref 5. dimension 'b' is measured at the maximum solder ball diameter. this drawing is for general information only. d a side view top view 8 solder balls bottom view 1 a b c d 2 (e1) e a1 ball pad corner (d1) 5. b a1 a2 d a1 ball pad corner e
15 at24c512 1116m?seepr?05/05 8cn1 ? lap 1150 e.cheyenne mtn blvd. colorado springs, co 80906 title drawing no. r rev. 8cn1 , 8-lead (8 x 5 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) b 8cn1 11/8/04 common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.36 0.41 0.46 1 d 7.90 8.00 8.10 e 4.90 5.00 5.10 e 1.27 bsc e1 0.60 ref l 0.62 .0.67 0.72 1 l1 0.92 0.97 1.02 1 note: 1. metal pad dimensions. 2. all exposed metal area shall have the following finished platings. ni: 0.0005 to 0.015 mm au: 0.0005 to 0.001 mm pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d
16 at24c512 1116m?seepr?05/05 8p3 ? pdip 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8 p 3 , 8 -le a d, 0. 3 00" wide body, pl as tic d ua l in-line p a ck a ge (pdip) 01/09/02 8 p 3 b note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to jedec dr a wing m s -001, v a ri a tion ba, for a ddition a l inform a tion. 2. dimen s ion s a a nd l a re me asu red with the p a ck a ge s e a ted in jedec s e a ting pl a ne g au ge g s - 3 . 3 . d, d1 a nd e1 dimen s ion s do not incl u de mold fl as h or protr us ion s . mold fl as h or protr us ion s s h a ll not exceed 0.010 inch. 4. e a nd ea me asu red with the le a d s con s tr a ined to b e perpendic u l a r to d a t u m. 5. pointed or ro u nded le a d tip s a re preferred to e as e in s ertion. 6. b 2 a nd b3 m a xim u m dimen s ion s do not incl u de d a m ba r protr us ion s . d a m ba r protr us ion s s h a ll not exceed 0.010 (0.25 mm). common dimen s ion s (unit of me asu re = inche s ) s ymbol min nom max note d d1 e e1 e l b 2 b a2 a 1 n ea c b3 4 plc s a ? ? 0.210 2 a2 0.115 0.1 3 0 0.195 b 0.014 0.01 8 0.022 5 b 2 0.045 0.060 0.070 6 b3 0.0 3 0 0.0 3 9 0.045 6 c 0.00 8 0.010 0.014 d 0. 3 55 0. 3 65 0.400 3 d1 0.005 ? ? 3 e 0. 3 00 0. 3 10 0. 3 25 4 e1 0.240 0.250 0.2 8 0 3 e 0.100 b s c ea 0. 3 00 b s c 4 l 0.115 0.1 3 0 0.150 2 top view s ide view end view
17 at24c512 1116m?seepr?05/05 8s2 ? eiaj soic 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 8s 2 , 8 -le a d, 0.209" body, pl as tic s m a ll o u tline p a ck a ge (eiaj) 10/7/0 3 8s 2 c common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note note s : 1. thi s dr a wing i s for gener a l inform a tion only; refer to eiaj dr a wing edr-7 3 20 for a ddition a l inform a tion. 2. mi s m a tch of the u pper a nd lower die s a nd re s in bu rr s a re not incl u ded. 3 . it i s recommended th a t u pper a nd lower c a vitie s b e e qua l. if they a re different, the l a rger dimen s ion s h a ll b e reg a rded. 4. determine s the tr u e geometric po s ition. 5. v a l u e s b a nd c a pply to p b / s n s older pl a ted termin a l. the s t a nd a rd thickne ss of the s older l a yer s h a ll b e 0.010 +0.010/ ? 0.005 mm. a 1.70 2.16 a1 0.05 0.25 b 0. 3 5 0.4 8 5 c 0.15 0. 3 5 5 d 5.1 3 5. 3 5 e1 5.1 8 5.40 2, 3 e 7.70 8 .26 l 0.51 0. 8 5 ? 0 8 e 1.27 b s c 4 end view s ide view e b a a1 d e n 1 c e1 ? l top view
18 at24c512 1116m?seepr?05/05 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. note: 10/7/0 3 8s 1 , 8 -le a d (0.150" wide body), pl as tic g u ll wing s m a ll o u tline (jedec s oic) 8s 1 b common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a1 0.10 ? 0.25 the s e dr a wing s a re for gener a l inform a tion only. refer to jedec dr a wing m s -012, v a ri a tion aa for proper dimen s ion s , toler a nce s , d a t u m s , etc. a 1. 3 5 ? 1.75 b 0. 3 1 ? 0.51 c 0.17 ? 0.25 d 4. 8 0 ? 5.00 e1 3 . 8 1 ? 3 .99 e 5.79 ? 6.20 e 1.27 b s c l 0.40 ? 1.27 ? 0 ? 8 ? top view end view s ide view e b d a a1 n e 1 c e1 l
19 at24c512 1116m?seepr?05/05 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
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